Across all sectors, industries, and geographies, demands continue for the electronic industry to provide products that are lighter, faster, smaller, multi-functional, more reliable, and more cost-effective. In order to meet these expanding requirements of so many and varied consumers, more electrical circuits need to be more highly integrated to provide the demanded functions. Across virtually all applications, there continues to be growing demand for reducing size, increasing performance, and improving features of integrated circuits.
The seemingly endless restrictions and requirements are no more visible than with products in our daily lives. Smaller and denser integrated circuits are required in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
As the demand grows for smaller electronic products with more features, manufacturers are seeking ways to include more features as well as reduce the size of the integrated circuits. However, increasing the density of integration in integrated circuits may be expensive and have technical limitations. Though technology continues its growth to once unimagined extents, practical limits of individual integrated circuits do exist.
To meet these needs, three-dimensional type integrated circuit packaging techniques have been developed and used. Packaging technologies are increasingly using smaller footprints with more circuits in three-dimensional packages. In general, package stacks made by stacking packages and stacked chip packages made by stacking chips in a package have been used.
In integrated circuit packaging, in addition to component reduction, surface mount technology has demonstrated an increase in semiconductor chip density on a single substrate or board, resulting from more compact designs and footprint and a significant increase in integrated circuit density. However, greater integrated circuit density is becoming significantly limited by the space available for the mounting of semiconductor dice on a carrier substrate.
Stack semiconductor packages are advanced packaging technology, which is characterized by stacking a plurality of chips in a single package structure, so as to desirably multiply operational performances and memory capacity for semiconductor packages.
However, when stacking a plurality of chips in a single package structure, the bonding wires may be subject to wire sagging or sweeping due to strong mold-flow impact of a molding compound. Wire sweep would cause electrical contact or short circuit between adjacent bonding wires or between bonding wires and chips, causing damage to the stacked semiconductor package.
Moreover, when stacking multiple chips on top of each other, different sets of bonding wires extend laterally to reach different areas on the substrate outside the underlying chips. This increases the occupied area on the substrate.
Furthermore, the wire loops of the bonding wires bonded to the overlying chip are adapted in elevation to allow the wire lateral extension to reach farther than the bonding wires bonded to the underlying chip. This increases the height or the thickness of the stacked integrated circuit packages.
In the Board on Chip (BOC) assembly, a first semiconductor device may be attached active face down on the surface of a substrate with bond wires extending through a substrate opening from bond pads on the bottom of the substrate to central bond pads on the active surface of the semiconductor device. A second similar semiconductor device is bonded back-to-back on the first semiconductor device. The central bond pads on the second semiconductor device require long bond wires to connect to the substrate at the periphery of the second semiconductor device. An encapsulant is used to cover the bond wires to prevent contamination.
A method for forming stacked semiconductor device assemblies, which enables the use of shorter bond wires, and a substrate smaller relative to the size of the semiconductor devices has been long sought. Similarly, a method for further reducing the overall height (thickness) of the BOC stacked structure has been long sought.
Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.